The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a method and structure for contact formation using doped silicon.
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by an insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of second conductivity type (P or N) into a semiconductor substrate of first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.
Once formed IGFETs must be wired together in order to complete functional circuits. The materials, methods, and processes of xe2x80x9cwiringxe2x80x9d the component parts together is generally referred to as metallization. Prior to the development of very large scale integration (VLSI)-level circuits, the primary metallization material was pure aluminum (Al). Today""s metallization processes, however, have evolved from the simple one level pure aluminum process.
Several objectives have influenced IGFET design and fabrication changes. These include; a drive for increased circuit density, an increase in the number of surface layers, and the miniaturization of individual components. The miniaturization of individual components equates to placing a greater number of IGFETs on a single chip. This in turn produces increased circuit density and yields greater functionality per chip. A further objective is to improve the performance, and particularly the speed, of the IGFET transistors. This pursuit is manifested by shorter conduction channel lengths and through efforts to obtain low contact resistivity at the IGFET junctions. These aspects offer increased IGFET speed and allow for a greater number of operations to be performed by the IGFET in less time. IGFETs are used in great quantity in computers where the push to obtain higher operation cycle speeds demands faster IGFET performance. In these efforts, it is desirable to keep costly IGFET fabrication steps to a minimum.
Contact resistance between the IGFET and different metallization layers presents a particularly difficult hurdle for further IGFET design evolution. The contact resistance is influenced by the materials, the substrate doping and the contact dimensions. The contact dimensions are typically referred to as the aspect ratio of the contact. The aspect ratio is given by the equation: Aspect Ratio=(Width of the opening)/(the Height of the opening), (AR=W/T). The smaller the contact size or the higher the aspect ratio of the contact opening, the higher the resistance. Modern dynamic random access memory (DRAM) design often necessitates IGFETs to be formed with high aspect ratio contact openings to accommodate other components of the device. The cumulative effect of all the individual contact resistances can dominate the conductivity of the metal system. In effect, contact resistance has become the dominant factor in ultra large scale integration (ULSI) metal system performance. Aluminum-silicon (Alxe2x80x94Si) contact resistance, along with its concomitant problems of electromigration and eutectic alloying have led to investigation of other contact materials for use in VLSI and ULSI metallization.
A continual need exists for creating improved junctions between the IGFET structures and subsequent metallization layers. Thus, it is desirable to uncover new material combinations and methods for processing the same which will reduce the contact resistivity between the IGFET device and subsequent metallization layers. Further, a method is desirable to achieve the above mentioned results while keeping costly fabrication steps to a minimum.
A method for forming a contact using doped silicon is provided. The method includes forming a contact opening in a surface layer on a silicon substrate. Then, a first contact material is deposited on and within the contact opening. A barrier metal is deposited on the first contact material. The method further includes annealing the contact and then depositing a second contact material on the barrier metal. In one embodiment, the first contact material is germanium (Ge) which is deposited to form an alloy with the silicon substrate.
In another embodiment, a device is provided which includes a contact formed of doped silicon. The device includes a contact opening within a surface layer on a silicon substrate. A first contact material is formed on and within the contact opening. The first contact material forms an alloy with the silicon substrate. A barrier metal couples to the first contact material. And, a second contact material couples to the barrier metal. The first contact material comprises germanium (Ge).
In another embodiment, an information handling system is provided. The information handling system includes; a central processing unit, a random access memory, and a system bus which communicatively couples the central processing unit to the random access memory. The information handling system further includes a contact formed of doped silicon. The contact has a contact opening within a surface layer on a silicon substrate. A first contact material is formed on and within the contact opening and the first contact material forms an alloy with the silicon substrate. A barrier metal couples to the first contact material. A second contact material coupling to the barrier metal.
In an alternative embodiment, a method for forming a contact is provided. The method includes forming a high aspect ratio contact opening in a surface layer on a silicon substrate. the surface layer is borophosphorus silicate glass (BPSG). An alloy material is deposited on and within the contact opening to reduce the aspect ratio of the contact opening. The method includes depositing an alloy of silicon-germanium (Sixe2x80x94Ge). Next, a barrier metal is deposited on the alloy material. And, finally a further contact material is deposited on the barrier metal.
In another embodiment, a device is provided, the device having a high aspect ratio contact opening within a surface layer on a silicon substrate. The device further includes, an alloy material formed on and within the contact opening to reduce the aspect ratio of the contact opening. There is a barrier metal coupling to the alloy material. And, a contact material couples to the barrier metal.
An alternative embodiment provides for an integrated circuit which has a central processing unit, a random access memory, a system bus which communicatively couples the central processing unit and the random access memory, and the device just previously recited.
Another embodiment, provides a method for forming a contact including forming a high aspect ratio contact opening in a surface layer on a silicon substrate, forming an oxide layer on and within the contact opening in the surface layer, and depositing an alloy material on the oxide layer and within the contact opening to reduce the aspect ratio of the contact opening.
In an alternative embodiment, a device is provided having a contact opening in a surface layer on a silicon substrate, an oxide layer on and within the contact opening in the surface layer; and an alloy material on the oxide layer and within the contact opening such that the aspect ratio of the contact opening is reduced.
Another embodiment, provides a method for forming a contact including forming a contact opening in a surface layer on a silicon substrate, forming an oxide layer on and within the contact opening in the surface layer, and depositing a germanium (Ge) contact within the contact opening in the silicon substrate and annealing to form an alloy with the substrate.
In an alternative embodiment, a device is provided having a contact opening in a surface layer on a silicon substrate, an oxide layer on and within the contact opening in the surface layer; and a germanium (Ge) contact formed within the contact opening in the silicon substrate. The germanium (Ge) contact forms an alloy with the silicon substrate.
Thus various embodiments are provided for fabricating a contact which result in multiple new structures. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through various steps and structures laid forth in the detailed description. The above advantages are incorporated with relatively few process steps.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.